The present invention relates to an improved storage logic array (SLA) circuit wherein the storage element is simplified resulting in a higher density SLA circuit chip.
There is much interest today in implementing custom or semi-custom digital circuit devices in a large scale or a very large scale integrated chip using a regular logic array structure. One such regular logic array structure is a programmable logic array (PLA) comprising, for example, a plurality of column input leads and a plurality of row output leads. The column leads carry a plurality of input signals and their complements. Any combination of the input leads can be coupled to the plurality of row output leads to form a number of conjugate terms (by providing a number of coupled column and row leads to an AND gate). The conjugate terms are then provided to OR gates to provide the output signals.
In some PLA's flip-flops have been added to the circuit to provide feedback from the outputs to the inputs. This provides increased range of application for the PLA but most PLA's suffer from inefficient utilization of the chip area within the AND and OR arrays because only a small fraction of available logic elements on the chip are actually used in typical designs.
One of the more powerful and interesting regular logic arrays, called storage logic arrays (SLA), is described in detail in an article in the IEEE Transactions on Computers entitled, "A Programmable Logic Approach for VLSI", by Suhas S. Patil and Terry A. Welch, Vol. C-28, No. 9, Sept. 1979, pages 594-601, hereby incorporated by reference as if specifically set forth herein. A SLA chip comprises a plurality of logical column circuits, each column circuit including: a storage cell, such as a set, reset flip-flop in the form of cross coupled logic gates; and four column leads disposed to be coupled to or to be decoupled from the flip-flop. The SLA chip further comprises a plurality of row circuits crossing over the logical column circuits, each row circuit disposed to be coupled to or decoupled from the input and output leads of each logical column circuit. Two of the column leads provide the set and reset commands, and the remaining two provide the Q and Q outputs. The set, reset flip-flop also requires the use of at least sic transistors for implementation. It is desirable to reduce the area of a chip used by the SLA circuit since, generally, with integrated circuits, smaller is better.